The present invention relates to a non-volatile semiconductor memory cell and its memory array and, more particularly, to a dual-bit floating-gate flash cell structure and its contactless flash memory arrays.
A stack-gate flash memory cell is known to be a one-transistor cell, in which a gate length of the cell can be defined by using a minimum feature size (F) of technology used. As a consequence, the stack-gate flash memory cell is often used in a high-density flash memory system. The stack-gate flash memory cell can be configured into different array architectures such as NAND, NOR, and AND, based on the basic logic function. For a NAND-type flash memory array, the stack-gate flash memory cells are connected in series through common source/drain diffusion regions. In general, a unit cell size of a NAND-type flash memory array is small, but the read speed is slow due to the series resistance of the configuration. For a NOR-type flash memory array, the read speed is faster, but the unit cell size is larger than that of a NAND-type flash memory array due to the bit-line contacts and the punch-through effect becomes a major concern for device scaling. For a AND-type flash memory array, the stack-gate flash memory cells are connected in parallel through the buried source/drain diffusion lines, the unit cell size is slightly larger than that of a NAND-type flash memory array and is smaller than that of a NOR-type flash memory array, and the read speed is faster than that of a NAND-type array and is slower than that of a NOR-type flash memory array. The stack-gate flash memory cells can be implemented to form a dual-bit flash memory cell by using a pair of stack-gate flash memory cells separated by a select-gate transistor to prevent the over-erase problem of the stack-gate structure. A typical example of a dual-bit flash memory cell is shown in FIG. 1A and FIG. 1B.
Referring now to FIG. 1A, two stack-gate cells 20G, 22G are separated by a select gate 24G and two common N+/Nxe2x88x92 diffusion lines 20A, 22A being acted as bit lines are formed in each outer side portion of the two gate-stack cells 20G, 22G. A top plan view of FIG.1A is shown in FIG. 1B, in which a polysilicon layer 28 being acted as a select-gate line is formed above the two common N+/Nxe2x88x92 diffusion lines 20A, 22A and the two control-gate lines 20C, 22C of the two stack-gate cells. From FIG. 1A and FIG. 1B, it is clearly seen that four masking photoresist steps are required to implement a dual-bit flash memory cell and the cell size of each bit is limited to 4F2. Moreover, there are several drawbacks as compared to existing stack-gate cell used in NAND, NOR and AND arrays: very high parasitic capacitances between the select-gate line 28 and the bit lines 20A, 22A; very high parasitic capacitances between the select-gate line 28 and the control-gate lines 20C, 22C of the stack-gate cells; alignment between the select gate line 28 and the floating-gates 22B, 20B is critical; isolation between the stack-gate cells in nearby select-gate lines is poor; and isolation between the select-gate lines in nearby control-gate lines is weak. It should be noted that poor isolation between nearby select-gate lines may result in erroneous data reading for a selected cell.
It is, therefore, an objective of the present invention to offer a dual-bit floating-gate cell structure having a cell size of each bit smaller than 4F2.
It is another objective of the present invention to provide good isolation for nearby dual-bit floating-gate cells under nearby word lines.
It is a further objective of the present invention to offer two array architectures for the dual-bit floating-gate cells with less masking photoresist steps.
The present invention discloses a dual-bit floating-gate flash cell structure and its contactless flash memory arrays being formed on a semiconductor substrate. The dual-bit floating-gate flash cell structure comprises a gate region being formed between a common-source region and a common drain region, wherein the gate region and the common-source/drain regions are patterned by a first masking photoresist step. The gate region comprises a pair of floating gates being formed on a pair of tunneling dielectric layers and defined by a pair of second sidewall dielectric spacers and a select-gate dielectric layer being formed between the pair of floating gates, wherein an implant region comprising a shallow implant region for threshold-voltage adjustment and a deep implant region for forming a punch-through stop is formed in a surface portion of the semiconductor substrate under the select-gate dielectric layer. The common source/drain region comprises a common-source/drain diffusion region or a pair of isolated source/drain diffusion regions; a pair of first sidewall dielectric spacers being formed over sidewalls of each of the common-source/drain regions and on a portion of the tunneling dielectric layer to form a shallow heavily-doped common-source/drain diffusion region within each of the common-source/drain diffusion regions or a shallow trench between the pair of first sidewall dielectric spacers for obtaining the pair of isolated source/drain diffusion regions; and an etched-back first planarized thick-oxide layer together with a pair of etched-back first sidewall dielectric spacers being formed in each of the common-source/drain regions. A word line over an intergate dielectric layer is formed over the pair of floating-gates and the select-gate dielectric layer in the gate region and the pair of etched-back first sidewall dielectric spacers and the etched-back first planarized thick-oxide layer in each of the common-source/drain regions, wherein the word line, the intergate dielectric layer and the pair of floating-gates are simultaneously patterned and etched by a second masking photoresist step and the semiconductor substrate in the gate region outside of the word line is implanted with doping impurities to form isolation implant regions or is anisotropically etched to form shallow trench isolation regions.
The dual-bit floating-gate cell structure as described is used to form two different contactless flash memory arrays: a contactless parallel common-source/drain diffusion bit-lines array and a contactless parallel isolated source/drain diffusion bit-lines array.
The contactless parallel common-source/drain diffusion bit-lines array comprises a plurality of gate regions being formed in parallel and alternately on a semiconductor substrate by using a first masking photoresist step, wherein each of the plurality of gate regions is located between common-source/drain regions; a common-source/drain diffusion region acted as a common-source/drain diffusion bit line being formed in a surface portion of the semiconductor substrate in each of the common-source/drain regions; a pair of etched-back first sidewall dielectric spacers being formed over a pair of tunneling dielectric layers in each of the common-source/drain regions; a shallow heavily-doped commonsource/drain diffusion region being formed by implanting doping impurities into a surface portion of the semiconductor substrate between a pair of first sidewall dielectric spacers in a self-aligned manner and within each of the common-source/drain diffusion regions; an etched-back first planarized thick-oxide layer being formed between the pair of etched-back first sidewall dielectric spacers in each of the common-source/drain regions; a plurality of paired floating-gates defined by a pair of second sidewall dielectric spacers being formed in each of the plurality of gate regions with a select-gate dielectric layer over an implant region being formed between the pair of floating gates; a plurality of word lines over a plurality of intergate dielectric layers being formed transversely to the common-source/drain regions and over the plurality of paired floating-gates and the select-gate dielectric layers in the plurality of gate regions and over a plurality of etched-back first sidewall dielectric spacers and the etched-back first planarized thick-oxide layers in the common-source/drain regions; and a plurality of isolation implant regions or a plurality of shallow trench isolation regions being formed in surface portions of the semiconductor substrate between the common-source/drain regions outside of the plurality of word lines. The implant region under the select-gate dielectric layer comprises a shallow implant region for threshold-voltage adjustment and a deep implant region for forming a punch-through stop.
The contactless parallel isolated source/drain diffusion bit-lines array comprises a plurality of gate regions being formed in parallel and alternately on a semiconductor substrate by using a first masking photoresist step, wherein each of the plurality of gate regions is located between common-source/drain regions; a pair of isolated source/drain diffusion regions defined by a pair of first sidewall dielectric spacers being separated by a shallow trench isolation region in each of the common-source drain regions; an etched-back first planarized thick-oxide layer being formed between a pair of etched-back first sidewall dielectric spacers in each of the common-source/drain regions; a plurality of paired floating-gates defined by a pair of second sidewall dielectric spacers being formed in each of the plurality of gate regions with a select-gate dielectric layer over an implant region being formed between the paired floating-gates; a plurality of word lines over a plurality of intergate dielectric layers being formed transversely to the isolated source/drain diffusion regions and over the plurality of paired floating-gates and the select-gate dielectric layers in the plurality of gate regions and a plurality of etched-back first sidewall dielectric spacers and the etched-back first planarized thick-oxide layers in the common-source/drain regions; and a plurality of isolation implant regions or a plurality of shallow trench isolation regions being formed in surface portions of the semiconductor substrate outside of the plurality of word lines and between the common-source/drain regions. The implant region under the select-gate dielectric layer comprises a shallow implant region for threshold-voltage adjustment and a deep implant region for forming a punch-through stop. dr
FIG. 1A and FIG. 1B show schematic diagrams of the prior art, in which FIG. 1A shows a cross-sectional view of a dual-bit floating-gate flash memory cell and FIG. 1B shows a top plan view of the dual-bit floating-gate flash memory cell shown in FIG. 1A.
FIG. 2A through FIG. 2I show process steps and their cross-sectional views for forming a dual-bit floating-gate cell structure and its contactless parallel common-source/drain diffusion bit-lines array of the present invention.
FIG. 3A shows a schematic top plan view of a contactless parallel common-source/drain diffusion bit-lines array of the present invention.
FIG. 3B through FIG. 3D show various cross-sectional views as indicated in FIG. 3A, in which a cross-sectional view along a B-Bxe2x80x2 line as indicated in FIG. 3A is shown in FIG. 3B; a cross-sectional view along a C-Cxe2x80x2 line as indicated in FIG. 3A is shown in FIG. 3C; and a cross-sectional view along a D-Dxe2x80x2 line as indicated in FIG. 3A is shown in FIG. 3D.
FIG. 3E shows a schematic circuit representation of a contactless parallel common-source/drain diffusion bit-lines array of the present invention.
FIG. 4A through FIG. 4C show simplified process steps after FIG. 2C and their cross-sectional views for forming a dual-bit floating-gate cell structure and its contactless parallel isolated source/drain diffusion bit-lines array of the present invention.
FIG. 5A shows a schematic top plan view of the contactless parallel isolated source/drain diffusion bit-lines array of the present invention.
FIG. 5B through FIG. 5E show various cross-sectional views as indicated in FIG. 5A, in which a cross-sectional view along a B-Bxe2x80x2 line as indicated in FIG. 5A is shown in FIG. 5B; a cross-sectional view along a C-Cxe2x80x2 line as indicated in FIG. 5A is shown in FIG. 5C; a cross-sectional view along a D-Dxe2x80x2 line as indicated in FIG. 5A is shown in FIG. 5D; and a cross-sectional view along a E-Exe2x80x2 line as indicated in FIG. 5A is shown in FIG. 5E.
FIG. 5F shows a schematic circuit representation of a contactless parallel isolated source/drain diffusion bit-lines array of the present invention.